Design of a LDO with High PSRR

Abstract One of the common ways to increase PSRR(power supply rejection ratio) LDO (low dropout linear regulator) is increasing gain error amplifier, but stability system will also be reduced. A new high amplifier designed push poles inside away from origin, which ensures and improves PSRR low frequency band. At TT process corner, range adjustable output voltage 1.361~1.860 V under simulation condition 27 °C. When power ranges 2.3 3.3 V, regulation rate 238.3 µV/V; load changes 0 20 mA, 9.6 µV/mA; current µA, ratio -97 dB@dc, phase margin whole circuit greater than 66 degrees. The chip verified in a 0.18 µm CMOS process. Setting stable at 1.8 only 1.9 mV, less 0.2%.